The present invention relates to a semiconductor device including metal interconnects and plugs connected to the metal interconnects, and a method for fabricating the same.
The processing dimension of the most advanced semiconductor devices currently mass-produced is 0.18 μm, which will be further reduced in the near future, and the processing dimension of the next generation will be definitely reduced to 0.15 μm, 0.13 μm and 0.1 μm successively. In such trend toward the dimensional reduction, alignment accuracy between a metal interconnect and a plug is preferably ±10% or less.
However, since metal interconnects are thus refined, it is difficult to realize the alignment accuracy of ±10% or less by employing lithography technique alone, and fine processing using a self-alignment method is indispensable.
Also, in currently used multi-layer interconnects, various techniques, such as a technique to use a material having a low dielectric constant k, namely, the so-called low-k material, as an interlayer insulating film and a technique to form an air gap between interconnects, have been developed in order to reduce interconnect delay.
Now, an example of a method for fabricating a semiconductor device including a plug and a metal interconnect by employing the self-alignment method developed for improving the alignment accuracy will be described with reference to FIGS. 17A through 17D, 18A through 18C, 19A through 19C and 20A through 20C.
First, as shown in FIG. 17A, an insulating film 11 of an insulating material is formed on a semiconductor substrate 10 by known chemical vapor deposition (CVD) or spin coating, and thereafter, a plug (not shown) connected to the semiconductor substrate 10 or an interconnect formed on the semiconductor substrate 10 is formed in the insulating film 11. The insulating film 11 is generally made from a silicon oxide film (with a dielectric constant k of approximately 4.3) or a low dielectric film having a dielectric constant lower than that of the silicon oxide film.
Next, as shown in FIG. 17B, a first barrier metal layer 12, a metal film 13 and a second barrier metal layer 14 are successively deposited on the insulating film 11, thereby forming a multi-layer metal film 15. The metal film 13 is made from an aluminum film deposited by known sputtering, and the first and second barrier metal layers 12 and 14 are deposited by the known sputtering and generally made from titanium nitride when the metal film 13 is made from an aluminum film.
Then, as shown in FIG. 17C, a first interlayer insulating film 16 of an insulating material is formed on the multi-layer metal film 15 by the CVD or spin coating, and then, a first resist pattern 17 is formed on the first interlayer insulating film 16 by known lithography.
Thereafter, as shown in FIG. 17D, the first interlayer insulating film 16 is dry etched by using the first resist pattern 17 as a mask, thereby forming via holes (via holes) 18 in the first interlayer insulating film 16.
Next, as shown in FIG. 18A, a conducting film 19 is deposited on the first interlayer insulating film 16 by the CVD so as to fill the via holes 18. The conducting film 19 is made from, for example, a tungsten film, and although not shown in the drawing, a barrier metal layer of a titanium film or a titanium nitride film is formed by the sputtering under the conducting film 19.
When the via hole 18 has an aspect ratio (a ratio of the depth to the diameter) higher than approximately 4, a void 20 is formed in the conducting film 19 within the via hole 18.
Then, a portion of the conducting film 19 present on the first interlayer insulating film 16 is removed by, for example, chemical mechanical polishing (CMP), so as to form plugs 21 as shown in FIG. 18B. Thereafter, the first interlayer insulating film 16 is dry etched so as to reduce the thickness of the first interlayer insulating film 16 as shown in FIG. 18C.
Subsequently, as shown in FIG. 19A, a second resist pattern 22 is formed on the first interlayer insulating film 16 with the reduced thickness, and then, the first interlayer insulating film 16 is dry etched by using the second resist pattern 22 as a mask, thereby forming a patterned first interlayer insulating film 16A as shown in FIG. 19B.
Next, the multi-layer metal film 15 is dry etched by using the plugs 21 and the patterned first interlayer insulating film 16A as a mask, thereby forming the multi-layer metal film 15 into metal interconnects 15A as shown in FIG. 19C. Since the plugs 21 and the metal interconnects 15A have a self-alignment structure in this manner, the positional shift between the plugs 21 and the metal interconnects 15A can be avoided.
The second resist pattern 22 is removed by ashing before or after the dry etching of the multi-layer metal film 15. Even when the second resist pattern 22 is removed after the dry etching of the multi-layer metal film 15, a portion of the second resist pattern 22 present on the plugs 21 is eliminated during the dry etching of the multi-layer metal film 15. Therefore, upper portions of the plugs 21 are slightly etched, and hence, openings 20a are formed in the upper portions of the voids 20.
Next, the insulating film 11 and the patterned first interlayer insulating film 16A are dry etched, thereby reducing the thicknesses of the insulating film 11 and the patterned first interlayer insulating film 16A as shown in FIG. 20A.
Then, as shown in FIG. 20B, a second interlayer insulating film 23 is deposited over the semiconductor substrate 10 by the CVD, thereby forming air gaps 24 between the metal interconnects 15A. Thereafter, the second interlayer insulating film 23 is planarized by the CMP as shown in FIG. 20C.
When the procedures of FIG. 17A through FIG. 20C are repeatedly carried out subsequently, a semiconductor device having a multi-layer interconnect structure including air gaps can be fabricated.
In the conventional method for fabricating a semiconductor device, however, when the via hole 18 has an aspect ratio higher than approximately 4, the voids 20 are formed within the plugs 21 as shown in FIG. 18B. Therefore, when the metal interconnects 15A having the air gaps 24 are formed, the complete openings 20a of the voids 20 are formed in the plugs 21 as shown in FIG. 20C.
Accordingly, the electric resistance between the plug 21 and an upper metal interconnect formed on the second interlayer insulating film 23 is largely increased, which causes a problem that the device characteristic is degraded.
In this case, when the electric resistance between the contact plug 21 and the upper metal interconnect is large beyond the limit, the reliability of the metal interconnect structure is largely lowered, and the semiconductor device cannot be operated in the worst case.
Furthermore, in the planarization of the second interlayer insulating film 23 by the CMP, an abrasive used in the CMP enters the voids 20, which causes a problem that the plugs 21 are corroded by the abrasive.